1. Field of the Invention
The present invention relates to a multilayer wiring arrangement and, more particularly, to a multilayer semiconductor structure and method of forming said structure which acts to suppress delamination and cracking of low dielectric constant interlayer insulating materials.
2. Background and Related Art
With the fabrication of semiconductor devices, increased speed, density and design complexity requirements have necessitated forming multilayer wiring structures on the surface of the semiconductor substrate in order to effectively interconnect the various electrical elements of the semiconductor device. In a multilayer wiring structure, a plurality of wiring level layers are separated by interlayer insulating films, and the interconnection of the respective wiring level layers is achieved by conductive members formed in vias in the interlayer insulating films. This wiring level integration of a manufacturing process is known as the back-end-of-line (BEOL).
The BEOL of a typical semiconductor manufacturing process uses inorganic oxide dielectric materials as the intralayer and interlayer insulating films between the wiring level conductors and via conductors. Typical dielectric materials used in the industry for such purpose are silicon dioxide, silica glass, and fluorinated silica glass. These are normally deposited either by chemical vapor deposition (CVD) or spin on glass (SOG) processes.
With increasing demand for higher speed and more dense semiconductor devices, fabrication techniques have required the use of organic dielectric materials as the interlayer insulating film. These organic dielectric materials have a lower dielectric constant (k) than inorganic dielectric materials. Low-k dielectric materials are usually applied by a spin coating process. The physical properties of low-k materials are quite different from those typically exhibited by inorganic oxide dielectric materials. For example, low-k dielectric materials have approximately an order of magnitude lower modulus of elasticity. Thus, a typical low-k material, such as SiLK(trademark), has a modulus of elasticity of 2.7 MPa while SiO2 has a modulus of elasticity of 72 MPa. Likewise, there is greater than an order of magnitude difference in hardness with SiLK(trademark) exhibiting a hardness of 0.25 GPA and SiO2 exhibiting a hardness of 8.7 GPA. Similarly, coefficients of thermal expansion (CTE) are markedly different with SiLK(trademark) having a CTE of 50xc3x9710xe2x88x926 per degrees C and SiO2 having a CTE of 3xc3x9710xe2x88x926 per degrees C.
As a result of these different properties, the BEOL wiring level integration process using low-k dielectric material is much more complex than that typically employed using inorganic dielectric materials. For example, a thin layer of hard material such as, silicon dioxide or silicon nitride is needed over a low-k dielectric material to make the low-k material compatible with chemical mechanical polishing (CMP) processes.
The use of low-k polymeric dielectric materials thus has thus created new problems over what was known in using inorganic dielectric materials. For example, low-k organic materials have substantially lower bond strength to the other materials employed in multilayered BEOL wiring structure as compared to traditional oxide dielectric materials.
In this regard, since oxide dielectric materials form a very strong interfacial bond, semiconductor chips based upon oxide dielectric materials are fairly resistant against mechanical and thermal stresses applied to the chip during the manufacturing process or reliability testing.
The lower bond strength at the interfaces associated with low-k dielectric materials increases the likelihood of delamination at the interfaces during BEOL processing, thermal cycling or other stress testing operations than what has traditionally occurred. This delamination may then cause cracking of the wiring layer of a semiconductor chip. For example, a small delamination at the edge of a device produced by the dicing process will propagate toward the center of the chip and, over time, cause device failure. Since the risk of delamination increases with the increased number of BEOL wiring levels, advanced devices with increased number of wiring levels are more prone to this critical problem.
In addition to mechanically induced stresses, such as, handling and dicing, similar stresses are also produced when using low-k dielectric materials in semiconductor devices due to the interfacial stress caused by the differences in modulus of elasticity and TCE when the device is exposed to variations in temperature. In this regard, the magnitude of the stress is not only a function of the TCE and modulus of silicon, but is also a function of the low-k dielectric material, the hard mask material, the metal conductor material, passivation material, packaging material, and the thickness and volume fraction of each material in the structure.
Accordingly, it is an object of the present invention to provide improved semiconductor device structure.
It is a further object of the present invention to provide a multilayer semiconductor device reinforcement structure and a method of making the same structure which structure inhibits delamination of the layers.
It is yet a further object of the present invention to provide an improved multilayer semiconductor device method and structure which allows the use of low-k organic dielectric material between layers of copper-based metallurgy with minimal delamination of layers and cracking of metallurgy.
It is still yet a further object of the present invention to provide an improved multilayer semiconductor structure using low-k dielectrical materials wherein a network or mesh of interconnected conductive lines and vias are employed around at least the periphery of the semiconductor device to thus anchor the complete BEOL fabricated multilayer structure and thereby inhibit delamination and cracking.
It is yet another object of the present invention to provide a multilayer semiconductor device with a mesh-like reinforcing structure electrically isolated from the active devices which structure mechanically ties together layers of low-k insulating films separating copper-based layers of metal and vias and is formed at the same time as BEOL processing.
In accordance with the present invention, there is provided a mesh-like reinforcing structure to improve the structural integrity of a multilayer semiconductor structure using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The structure is such as to anchor the entire BEOL active device wiring integration metallization pattern and is formed during the normal BEOL device wiring level integration process. The mesh-like reinforcing structure may be fabricated on the periphery of the device, such as a chip, or within any open region of the device which may require anchoring to prevent delamination.